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ltc 6405 1 6405fb for more information www.linear.com/6405 l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. features a pplications description 2.7ghz, 5v, low noise, rail-to-rail input differential amplifier/driver the lt c ? 6405 is a very low noise, low distortion, fully differential input/output amplifier optimized for 5 v, single supply operation. the ltc6405 input common mode range is rail-to-rail, while the output common mode voltage is independently adjustable by applying a voltage on the v ocm pin. this makes the ltc6405 ideal for level shifting signals with a wide common mode range for driving 12-bit to 16-bit single supply, differential input adcs. a 2.7 ghz gain-bandwidth product results in 65 db linearity for 50 mhz input signals. the ltc6405 is unity gain stable and the closed- loop bandwidth extends from dc to 800mhz. the output voltage swing extends from near-ground to 4v, to be compatible with a wide range of adc converter input requirements. the ltc6405 draws only 18 ma, and has a hardware shutdown feature which reduces current consumption to 400a. the ltc6405 is available in a compact 3 mm 3mm 16 - pin leadless qfn package, as well as an 8- lead msop package, and operates over a C40c to 85c temperature range. single-ended input to differential output with common mode level shifting n low noise: 1.6nv/ hz rti n low power: 18ma at 5v n low distortion (hd2/hd3): C82 dbc/C65dbc at 50mhz, 2v p-p C97 dbc/C91dbc at 25mhz, 2v p-p n rail-to-rail differential input n 4.5 v to 5.25v supply voltage range n fully differential input and output n adjustable output common mode voltage n 800mhz C3db bandwidth with a v = 1 n gain-bandwidth product: 2.7ghz n low power shutdown n available in 8-lead msop and 16-lead 3mm 3mm 0.75mm qfn packages n differential input adc driver n single-ended to differential conversion n level-shifting ground-referenced signals n level-shifting v cc -referenced signals n high-linearity direct conversion receivers input noise density vs input common mode voltage t ypical a pplication ? + 200 5v v ocm 2.5v 0v 6405 ta01 v s 1v p-p 200 0.1f 196 ltc6405ud 0.01f 1.8pf 50 signal generator 61.9 221 2.5v 1v p-p 2v p-p 1.8pf 6405 ta01b 2 3.53 0.5 1 1.5 2.5 0 4.54 5 4 3 2 1 0 4 3 2 1 0 v s = 5v noise measured at f = 1mhz i n e n input voltage noise density (nv/ hz) input current noise density (pa/ hz) input common mode voltage (v)
ltc 6405 2 6405fb for more information www.linear.com/6405 a bsolute maxi m u m r atings total supply voltage (v + to v C ) ................................ 5. 5 v input current (+ in , C in , v ocm , shdn , v tip ) ( note 2) ............ 1 0 ma output short - circuit duration ( note 3) ............ ind efinite operating temperature range ( note 4) ............................................... C 40 c to 85 c (note 1) lead free finish tape and reel part marking* package description specified temperature range ltc6405cms8e#pbf ltc6405cms8e#trpbf ltdkn 8-lead plastic msop 0c to 70c ltc6405ims8e#pbf ltc6405ims8e#trpbf ltdkn 8-lead plastic msop C40c to 85c ltc6405cud#pbf ltc6405cud#trpbf ldkp 16-lead (3mm 3mm) plastic qfn 0c to 70c ltc6405iud#pbf ltc6405iud#trpbf ldkp 16-lead (3mm 3mm) plastic qfn C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ or d er in f or m ation 1 2 3 4 top view ms8e package 8-lead plastic msop 1 2 3 4 ?in v ocm v + +out 8 7 6 5 +in shdn v ? ?out 9 t jmax = 150c, ja = 40c/w, jc = 10c/w exposed pad (pin 9) is v C , must be soldered to pcb 16 17 15 14 13 5 6 7 8 top view ud package 16-lead (3mm 3mm) plastic qfn 9 10 11 12 4 3 2 1 shdn v + v ? v ocm v ? v + v + v ? nc +in ?out ?outf v tip ?in +out +outf t jmax = 150c, ja = 68c/w, jc = 4.2c/w exposed pad (pin 17) is v C , must be soldered to pcb p in c on f iguration specified temperature range ( note 5) ltc 6405 i ............................................. C 40 c to 85 c ltc 6 405 c ................................................ 0 c to 70 c junction temperature ........................................... 15 0 c storage temperature range .................. C 65 c to 150 c
ltc 6405 3 6405fb for more information www.linear.com/6405 symbol parameter conditions min typ max units v osdiff differential offset voltage (input referred) v icm = 5v (note 12) v icm = 2.5v v icm = 0v (note 12) l l l 1 0.5 1 7 3.5 7 mv mv mv ?v osdiff /?t differential offset voltage drift (input referred) v icm = 5v (note 12) v icm = 2.5v v icm = 0v (note 12) l l l 1.5 1 3 v/c v/c v/c i b input bias current (note 6) v icm = 5v v icm = 2.5v v icm = 0v l C24 8 C7 C14 a a a i os input offset current (note 6) v icm = 5v v icm = 2.5v v icm = 0v l 0.5 0.5 0.5 4 a a a r in input resistance common mode differential mode 230 3.5 k k c in input capacitance differential 1 pf e n differential input referred noise voltage density f = 1mhz, not including r i /r f noise 1.6 nv/hz i n input noise current density f = 1mhz, not including r i /r f noise 2.4 pa/hz e nvocm input referred common mode output noise voltage density f = 1mhz 9.5 nv/hz v icmr (note 7) input signal common mode range op-amp inputs l v C v + v cmrri (note 8) input common mode rejection ratio (input referred) ?v icm /?v osdiff v icm from 0v to 5v l 50 75 db cmrrio (note 8) output common mode rejection ratio (input referred) ?v ocm /?v osdiff v ocm from 0.5v to 3.9v l 50 75 db psrr (note 9) differential power supply rejection (?v s /?v osdiff ) v s = 4.5v to 5.25v l 50 75 db psrrcm (note 9) output common mode power supply rejection (?v s /?v oscm ) v s = 4.5v to 5.25v l 55 70 db g cm common mode gain (?v outcm /?v ocm ) v ocm from 0.5v to 3.9v l 1 v/v ?g cm common mode gain error 100 ? (g cm C 1) v ocm from 0.5v to 3.9v l 0.25 0.8 % bal output balance (?v outcm /?v outdiff ) ?v outdiff = 2v single-ended input differential input l l C60 C65 C40 C40 db db v oscm common mode offset voltage (v outcm C v ocm ) l 6 15 mv ?v oscm /?t common mode offset voltage drift l 20 v/c v outcmr (note 7) output signal common mode range (voltage range for the v ocm pin) l 0.5 3.9 v r invocm input resistance, v ocm pin l 13 19 25 k v ocm self-biased voltage at the v ocm pin v ocm = open l 2.35 2.5 2.65 v v out output voltage, high, +out/Cout pins i l = 0 i l = C5ma l l 3.9 3.85 4 3.95 v v output voltage, low, +out/Cout pins i l = 0 i l = 5ma l l 0.3 0.42 0.45 0.54 v v i sc output short-circuit current, +out/Cout pins (note 10) l 40 60 ma d c e lectrical c haracteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 5v, v C = 0v, v cm = v ocm = v icm = 2.5v, v shdn = open, circuit component values in figure 1 used, unless otherwise noted. v s is defined as (v + C v C ). v outcm is defined as (v +out + v Cout )/2. v icm is defined as (v +in + v Cin )/2. v outdiff is defined as (v +out C v Cout ).
ltc 6405 4 6405fb for more information www.linear.com/6405 symbol parameter conditions min typ max units a vol large-signal open loop voltage gain 90 db v s supply voltage range l 4.5 5.25 v i s supply current l 18 23 ma i shdn supply current in shutdown v shdn = 0v l 0.4 1 ma r shdn shdn pull-up resistor v shdn = 0v to 0.5v l 30 50 70 k v il shdn input logic low l 1.25 1.8 v v ih shdn input logic high l 2 2.55 v t on turn-on time 200 ns t off turn-off time 50 ns ac e lectrical c haracteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 5v, v C = 0v, v cm = v ocm = v icm = 2.5v, v shdn = open, r load = 400, circuit component values in figure 2 used, unless otherwise noted. v s is defined as (v + C v C ). v icm is defined as (v +in + v Cin )/2. v outdiff is defined as (v +out C v Cout ). symbol parameter conditions min typ max units sr slew rate differential output 690 v/s gbw gain-bandwidth product f test = 27mhz 2.7 ghz f C3db C3db frequency (see figure 2) qfn package msop package 500 400 800 750 mhz mhz 50mhz distortion differential input, v outdiff = 2v p-p (note 13) v ocm = 2.5v, v s = 5v 2nd harmonic 3rd harmonic l C80 C64 C53 dbc dbc v ocm = 2.5v, v s = 5v, r load = 800 2nd harmonic 3rd harmonic C82 C66 dbc dbc v ocm = 2.5v, v s = 5v, r load = 800, r i = r f = 499 2nd harmonic 3rd harmonic C82 C64 dbc dbc 50mhz distortion single-ended input, v outdiff = 2v p-p (note 13) v ocm = 2.5v, v s = 5v, r load = 800, r i = r f = 499 2nd harmonic 3rd harmonic C72 C77 dbc dbc 3rd-order imd at 49.5mhz, 50.5mhz v outdiff = 2v p-p envelope, r load = 800 C63 dbc equivalent oip3 at 50mhz (note 11) r load = 800 35.5 dbm t s settling time v outdiff = 2v step 1% settling 0.1% settling 6 11 ns ns nf noise figure at 50mhz shunt-terminated to 50, r s = 50 z in = 200 (r i = 100, r f = 300) 14.4 7.5 db db d c e lectrical c haracteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 5v, v C = 0v, v cm = v ocm = v icm = 2.5v, v shdn = open, circuit component values in figure 1 used, unless otherwise noted. v s is defined as (v + C v C ). v outcm is defined as (v +out + v Cout )/2. v icm is defined as (v +in + v Cin )/2. v outdiff is defined as (v +out C v Cout ).
ltc 6405 5 6405fb for more information www.linear.com/6405 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: input pins (+in, Cin, v ocm , shdn and v tip ) are protected by steering diodes to either supply. if the inputs should exceed either supply voltage, the input current should be limited to less than 10ma. in addition, the inputs +in, Cin are protected by a pair of back-to-back diodes. if the differential input voltage exceeds 1.4v, the input current should be limited to less than 10ma. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely. note 4: the ltc6405c/ltc6405i are guaranteed functional over the operating temperature range C40c to 85c. note 5: the ltc6405c is guaranteed to meet specified performance from 0c to 70c. the ltc6405c is designed, characterized, and expected to meet specified performance from C40c to 85c but is not tested or qa sampled at these temperatures. the ltc6405i is guaranteed to meet specified performance from C40c to 85c. note 6: input bias current is defined as the average of the input currents flowing into the inputs (Cin, and +in). input offset current is defined as the difference between the input currents (i os = i b + C i b C ). note 7: input common mode range is tested using the test circuit of figure 1 by taking 3 measurements of differential gain with a 1vdc differential output with v icm = 0v; v icm = 2.5v; v icm = 5v, verifying that the differential gain has not deviated from the v icm = 2.5v case by more than 0.5%, and that the common mode offset (v oscm ) has not deviated from the common mode offset at v icm = 2.5v by more than 35mv. the voltage range for the output common mode range is tested using the test circuit of figure 1 by applying a voltage on the v ocm pin and testing at both v ocm = 2.5v and at the electrical characteristics table limits to verify that the common mode offset (v oscm ) has not deviated by more than 20mv from the v ocm = 2.5v case. note 8: input cmrr is defined as the ratio of the change in the input common mode voltage at the pins +in or Cin to the change in differential input referred voltage offset. output cmrr is defined as the ratio of the change in the voltage at the v ocm pin to the change in differential input referred voltage offset. this specification is strongly dependent on feedback ratio matching between the two outputs and their respective inputs, and it is difficult to measure actual amplifier performance. (see the effects of resistor pair mismatch in the applications information section of this data sheet.) for a better indicator of actual amplifier performance independent of feedback component matching, refer to the psrr specification. note 9: differential power supply rejection (psrr) is defined as the ratio of the change in supply voltage to the change in differential input referred voltage offset. common mode power supply rejection (psrrcm) is defined as the ratio of the change in supply voltage to the change in the common mode offset, v outcm C v ocm . note 10: extended operation with the output shorted may cause the junction temperature to exceed the 150c limit. note 11: because the ltc6405 is a feedback amplifier with low output impedance, a resistive load is not required when driving an adc. therefore, typical output power can be very small in many applications. in order to compare the ltc6405 with rf style amplifiers that require 50 load , the output voltage swing is converted to dbm as if the outputs were driving a 50 load. for example, 2v p-p output swing is equal to 10dbm using this convention. note 12: includes offset/drift induced by feedback resistors mismatch. see the applications information section for more details. note 13: qfn package onlyrefer to datasheet curves for msop package numbers. e lectrical c haracteristics
ltc 6405 6 6405fb for more information www.linear.com/6405 t ypical p er f or m ance c haracteristics supply current vs supply voltage supply current vs shdn voltage shutdown supply current vs supply voltage differential input referred offset voltage vs temperature differential input referred offset voltage vs input common mode voltage common mode offset voltage vs temperature temperature (c) ?50 ?1.0 differential v os (mv) ?0.6 ?0.2 0.2 ?25 0 25 50 75 0.6 1.0 ?0.8 ?0.4 0 0.4 0.8 100 6405 g01 v s = 5v v ocm = 2.5v v icm = 2.5v r i = r f = 200 five representative units input common mode voltage (v) ?1.0 differential v os (v) ?0.6 ?0.2 0.2 0.6 1.0 ?0.8 ?0.4 0 0.4 0.8 6405 g02 v s = 5v v ocm = 2.5v r i = r f = 200 0.1% feedback network resistors represent- ative unit 0 3.5 1 2 0.5 4.5 1.5 2.5 4 3 5 t a = ?40c t a = 0c t a = 25c t a = 70c t a = 85c temperature (c) ?50 2 common mode offset voltage (mv) 4 6 8 ?25 0 25 50 75 9 3 5 7 100 6405 g03 v s = 5v v ocm = 2.5v v icm = 2.5v five representative units supply voltage (v) 6405 g04 total supply current (ma) 20 15 10 5 0 2 3.53 0.5 1 1.5 2.5 0 4.54 5 5.5 v shdn = open t a = ?40c t a = 0c t a = 25c t a = 70c t a = 85c shdn voltage (v) 6405 g05 total supply current (ma) 20 15 10 5 0 2 3.53 0.5 1 1.5 2.5 0 4.54 5 v s = 5v t a = ? 40c t a = 0c t a = 25c t a = 70c t a = 85c supply voltage (v) 6405 g06 shutdown supply current (a) 600 500 300 100 400 200 0 2 3.53 0.5 1 1.5 2.5 0 4.54 5 5.5 v shdn = v ? t a = ? 40c t a = 0c t a = 25c t a = 70c t a = 85c
ltc 6405 7 6405fb for more information www.linear.com/6405 t ypical p er f or m ance c haracteristics input noise density vs frequency input noise density vs input common mode voltage differential slew rate vs temperature differential output impedance vs frequency cmrr vs frequency differential psrr vs frequency temperature (c) ?50 600 slew rate (v/s) 640 680 ?25 0 25 50 75 720 620 660 700 100 6405 g09 v s = 5v frequency (mhz) 6405 g11 cmrr (db) v s = 5v v ocm = 2.5v r i = r f = 200?, c f = 1.8pf 0.1% feedback network resistors 90 80 20 30 40 50 60 70 1 100 10 1000 2000 frequency (mhz) 6405 g10 output impedance () v s = 5v r i = r f = 200? 1000 0.01 0.1 1 10 100 1 100 10 1000 2000 frequency (mhz) 6405 g12 psrr (db) v s = 5v 80 70 10 20 30 40 50 60 1 100 10 1000 2000 frequency (hz) 1k 100k 10m 1m 100 10k 6405 g07 1 10 100 1 10 100 v s = 5v v icm = 2.5v i n e n input voltage noise density (nv/ hz) input current noise density (pa/ hz) 6405 g08 2 3.53 0.5 1 1.5 2.5 0 4.54 5 4 3 2 1 0 4 3 2 1 0 v s = 5v noise measured at f = 1mhz i n e n input voltage noise density (nv/ hz) input current noise density (pa/ hz) input common mode voltage (v)
ltc 6405 8 6405fb for more information www.linear.com/6405 frequency response vs closed loop gain frequency response vs load capacitance frequency response vs input common mode voltage t ypical p er f or m ance c haracteristics a v = 10 a v = 5 a v = 20 a v = 100 a v = 2 a v = 1 frequency (mhz) 6405 g16 gain (db) v s = 5v v ocm = v icm = 2.5v r load = 400? 50 40 30 20 10 0 ?50 ?40 ?30 ?20 ?10 1 100 10 1000 2000 a v (v/v) c f (pf) r i (? ) r f (?) 1 2 5 10 20 100 200 200 200 200 200 200 200 400 1k 2k 4k 20k 1.8 1.5 0.6 0.2 0 0 frequency (mhz) 6405 g17 gain (db) v s = 5v v ocm = v icm = 2.5v r load = 400? r i = r f = 200?, c f = 1.8pf capacitor values are from each output to ground. no series resistors are used. 30 20 10 0 ?60 ?50 ?40 ?30 ?20 ?10 c l = 0pf c l = 2pf c l = 3pf c l = 4.7pf c l = 10pf 1 100 10 1000 2000 frequency (mhz) 6405 g18 gain (db) v s = 5v v ocm = 2.5v r load = 400? r i = r f = 200?, c f = 1.8pf 10 5 0 ?5 ?40 ?35 ?30 ?20 ?10 ?25 ?15 v icm = 0v v icm = 0.5v v icm = 1.25v v icm = 2.5v v icm = 4v v icm = 5v 1 100 10 1000 2000 small signal step response large signal step response overdriven output transient response 6405 g13 10ns/div 20mv/div +out ?out v s = 5v v ocm = v icm = 2.5v r load = 400 ? r i = r f = 200? c f = 1.8pf c l = 0pf 6405 g14 10ns/div v s = 5v r load = 400? v in = 2v p-p , differential +out ?out 0.2v/div 100ns/div voltage (v) 3.0 3.5 4.0 2.5 2.0 0.5 0 1.5 4.5 1.0 6405 g15 v s = 5v v ocm = 2.5v r load = 400? to ground per output ?out +out (qfn package)
ltc 6405 9 6405fb for more information www.linear.com/6405 harmonic distortion vs frequency harmonic distortion vs input common mode voltage harmonic distortion vs input amplitude frequency (mhz) 1 ?120 distortion (dbc) ?110 ?100 ?80 ?60 10 100 ?30 ?40 ?90 ?70 ?50 6405 g19 v s = 5v v ocm = v icm = 2.5v v tip = open (2.8v) r load = 800?, v outdiff = 2v p-p differential inputs hd3 r i = r f = 200? hd3 r i = r f = 499? hd2 r i = r f = 499? hd2 r i = r f = 200 ? input common mode voltage (v) 6405 g20 distortion (dbc) v s = 5v v ocm = 2.5v v tip = open (2.8v) f in = 50mhz r load = 800 ? v outdiff = 2v p-p differential inputs ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 32.521.5 54.543.5 10.5 hd2 hd3 r i = r f = 200? r i = r f = 499? r i = r f = 200? r i = r f = 499? input amplitude (dbm) 6405 g21 distortion (dbc) v s = 5v v ocm = v icm = 2.5v v tip = open (2.8v) f in = 50mhz r load = 800? r i = r f = 200? differential inputs hd3 hd2 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?2 86420 ?4 (0.4v p-p ) 10 (2v p-p ) t ypical p er f or m ance c haracteristics harmonic distortion vs frequency harmonic distortion vs input common mode voltage harmonic distortion vs input amplitude intermodulation distortion vs frequency intermodulation distortion vs input common mode voltage intermodulation distortion vs input amplitude input common mode voltage (v) 6405 g23 distortion (dbc) v s = 5v v ocm = 2.5v v tip = 2.35v f in = 50mhz r load = 800? r i = r f = 499? v outdiff = 2v p-p single-ended input ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 32.521.5 54.543.5 10.5 hd2 hd3 frequency (mhz) 6405 g22 distortion (dbc) v s = 5v v ocm = v icm = 2.5v v tip = 2.35v r load = 800? v outdiff = 2v p-p single-ended input ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?110 ?100 hd2, r i = r f = 200? hd2, r i = r f = 499? hd3, r i = r f = 200? hd3, r i = r f = 499? 1 100 10 input common mode voltage (v) 6405 g26 third order imd (dbc) v s = 5v v ocm = 2.5v v tip = open (2.8v) f in = 50mhz r load = 800 ? r i = r f = 200? 2 tones, 1 mhz tone spacin g, 2v p-p composite differential inputs ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 32.521.5 54.543.5 10.5 input amplitude (dbm) 6405 g24 distortion (dbc) v s = 5v v ocm = v icm = 2.5v v tip = 2.35v f in = 50mhz r load = 800? r i = r f = 499? single-ended input hd2 hd3 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?2 86420 ?4 (0.4v p-p ) 10 (2v p-p ) input amplitude (dbm) 6405 g27 third order imd (dbc) v s = 5v v ocm = v icm = 2.5v v tip = open (2.8v) f in = 50mhz r load = 800? r i = r f = 200? 2 tones, 1mhz tone spacing differential inputs ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?2 86420 ?4 (0.4v p-p ) 10 (2v p-p ) frequency (mhz) 6405 g25 third order imd (dbc) v s = 5v v ocm = v icm = 2.5v v tip = open (2.8v) r load = 800? r i = r f = 200? 2 tones, 1mhz tone spacing, 2v p-p composite differential inputs ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?110 ?100 1 100 10 (qfn package)
ltc 6405 10 6405fb for more information www.linear.com/6405 t ypical p er f or m ance c haracteristics harmonic distortion vs frequency harmonic distortion vs input amplitude frequency response vs load capacitance harmonic distortion vs frequency harmonic distortion vs input amplitude frequency (mhz) 6405 g28 gain (db) v s = 5v v ocm = v icm = 2.5v r load = 400? r i = r f = 300?, c f = 1pf capacitor values are from each output to ground. no series resistors are used. 30 20 10 0 ?50 ?40 ?30 ?20 ?10 c l = 10pf 1 100 10 1000 2000 c l = 0pf frequency (mhz) 6405 g29 distortion (dbc) v s = 5v v ocm = v icm = 2.5v v tip = open (2.8v) r load = 800? r i = r f = 300? v outdiff = 2v p-p differential inputs ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?110 ?100 hd3 hd2 1 100 10 input amplitude (dbm) 6405 g30 distortion (dbc) v s = 5v v ocm = v icm = 2.5v v tip = open (2.8v) f in = 50mhz r load = 800? r i = r f = 300? differential inputs hd2 hd3 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?2 86420 ?4 (0.4v p-p ) 10 (2v p-p ) frequency (mhz) 6405 g31 distortion (dbc) v s = 5v v ocm = v icm = 2.5v v tip = open (2.8v) r load = 800? r i = r f = 300? v outdiff = 2v p-p single-ended input ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?110 ?100 hd3 hd2 1 100 10 input amplitude (dbm) 6405 g32 distortion (dbc) hd2 hd3 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?2 86420 ?4 (0.4v p-p ) 10 (2v p-p ) v s = 5v v ocm = v icm = 2.5v v tip = open (2.8v) f in = 50mhz r load = 800? r i = r f = 300? single-ended input (msop package)
ltc 6405 11 6405fb for more information www.linear.com/6405 pin f unctions v ocm (pin 2/pin 4): output common mode reference voltage. the voltage on v ocm sets the output common mode voltage level ( which is defined as the average of the voltages on the + out and C out pins). the v ocm voltage is internally set by a resistive divider between the supplies, developing a default voltage potential of 2.5 v with a 5v supply. the v ocm pin can be over-driven by an external voltage capable of driving the 19 k thevenin equivalent impedance presented by the pin. the v ocm pin should be bypassed with a high quality ceramic bypass capacitor of at least 0.01 f, to minimize common mode noise from being converted to differential noise by impedance mismatches both externally and internally to the ic. v + (pin 3/pins 2, 10, 11): v C (pin 6/pins 3, 9, 12): power supply pins. it is critical that close attention be paid to supply bypassing. for single supply applications, it is recommended that a high quality 0.1 f surface mount ceramic bypass capacitor be placed between v + and v C with direct short connections. in addition, v C should be tied directly to a low impedance ground plane with minimal routing. for dual ( split) power supplies, it is recommended that additional high quality, 0.1 f ceramic capacitors are used to bypass v + to ground and v C to ground, again with minimal routing. for driving large loads (<200), additional bypass capacitance may be needed for optimal performance. keep in mind that small geometry ( e.g ., 0603 or smaller) surface mount ceramic capacitors have a much higher self resonant frequency than do leaded capacitors, and perform best in high speed applications. +out, Cout (pins 4, 5/pins 7, 14): unfiltered output pins. besides driving the feedback network, each pin can drive an additional 50 to ground with typical short circuit current limiting of 60 ma. each amplifier output is designed to drive a load capacitance of 5 pf. larger capacitive loads should be decoupled with at least 15 resistors from each output. v tip (pin 5) qfn only: this pin can normally be left float- ing. it determines which pair of input transistors ( npn or pnp or both) is sensing the input signal. the v tip pin is set by an internal resistive divider between the supplies, developing a default 2.8 v voltage with a 5 v supply. v tip has a thevenin equivalent resistance of approximately 17k and can be over-driven by an external voltage. the v tip pin should be bypassed with a high quality ceramic bypass capacitor of at least 0.01 f. see the applications information section for more details. shdn (pin 7/pin 1): when shdn is floating or directly tied to v + , the ltc6405 is in the normal ( active) operating mode. when the shdn pin is connected to v C , the ltc6405 enters into a low power shutdown state with hi-z outputs. + in, Cin ( pins 8, 1/pins 15, 6): noninverting and inverting input pins of the amplifier, respectively. for best perfor- mance, it is highly recommended that stray capacitance be kept to an absolute minimum by keeping printed circuit connections as short as possible. +outf, Coutf (pins 8, 13) qfn only: filtered output pins. these pins have a series rc network (r = 50, c = 3.75 pf) connected between the filtered and unfiltered outputs. see the applications information section for more details. nc (pin 16) qfn only: no connection. this pin is not connected internally. exposed pad (pin 9/pin 17): tie the bottom pad to v C . if split supplies are used, do not tie the pad to ground. (msop/qfn)
ltc 6405 12 6405fb for more information www.linear.com/6405 v + 50 1.25pf 1.25pf 1.25pf 50 v ? v + v ? ? + 1 5 v tip 6 ?in 7 +out 8 +outf 16 nc 15 +in 14 ?out 13 ?outf 2 v + 3 v ? v + v + v + v ? 4 v ocm 12 v ? 6405 bd02 11 v + 10 v + 9 v ? v + v ? v ? v ? shdn 37k 37k 30k 38k block d iagra m s ltc6405 block diagram/pinout in msop package ltc6405 block diagram/pinout in qfn package v + v ? v + v ? ? + 1 ?in 2 v ocm 3 v + v + 4 +out 8 +in 7 6 v ? v ? 5 ?out 37k 37k 6405 bd01 shdn
ltc 6405 13 6405fb for more information www.linear.com/6405 applications in f or m ation figure 1. dc test circuit ? + 1 shdn 5 6 ?in 7 +out 8 +outf 16 15 +in v tip nc 14 ?out 13 ?outf v ?outf r f c f v +outf v ?out v +out 2 v + 3 v ? v + v ? v + v ? 4 v ocm v shdn v vocm v ocm 12 v ? 11 v + 10 v + 9 v ? v ? v ? v ? c f v ? v ? 6405 f01 ltc6405 shdn 0.1f 0.01f v cm r f r i r i r bal 100k r bal 100k + ? v inp ? + v inm v ?in v +in v outcm v + 0.1f v ? 0.1f 0.1f 0.1f 1.25pf 1.25pf 1.25pf 0.1f 0.01f 50 50 (r i , r f : 0.1% resistors) *to optimize the high frequency performance for the pin configuration of the ltc6405 in the small msop package, a feedback resistance of at least 300 is recommended. package msop* qfn default values c f 1.0pf 1.8pf r i 300 200 r f 300 200 functional description the ltc6405 is a small outline, wideband, low noise, and low distortion fully-differential amplifier with accurate output phase balancing. the ltc6405 is optimized to drive low voltage, single-supply, differential input analog- to-digital converters ( adcs). the ltc6405 input common mode range is rail-to-rail, while the output common mode voltage is independently adjustable by applying a voltage on the v ocm pin. the output voltage swing extends from near-ground to 4 v, to be compatible with a wide range of adc converter input requirements. this makes the ltc6405 ideal for level shifting signals with a wide common mode range for driving 12- bit to 16- bit single supply, differential input adcs. the differential output allows for twice the signal swing in low voltage systems when compared to single-ended output amplifiers. the balanced differential nature of the amplifier also provides even-order harmonic distortion cancellation, and less susceptibility to common mode noise (like power supply noise). the ltc6405 can be used as a single ended input to differential output amplifier , or as a differential input to differential output amplifier. the ltc6405 output common mode voltage, defined as the average of the two output voltages, is independent of the input common mode voltage, and is adjusted by apply- ing a voltage on the v ocm pin. if the pin is left open, there is an internal resistive voltage divider, which develops a potential of 2.5v ( if the supply is 5 v). it is recommended that a high quality ceramic cap is used to bypass the v ocm pin to a low impedance ground plane. the ltc6405s internal common mode feedback path forces accurate output phase balancing to reduce even order harmonics, and centers each individual output about the potential set by the v ocm pin. v outcm = v ocm = v + out + v ?out 2
ltc 6405 14 6405fb for more information www.linear.com/6405 a pplications i n f or m ation figure 2. ac test circuit (C3db bw testing) 0.01f ? + 1 shdn 5 6 7 8 16 15 nc 14 13 2 v + 3 v ? v + v ? v + v ? 4 v ocm v shdn v vocm v ocm 12 v ? 11 v + 10 v + 9 v ? v ? v ? v ? v ? v ? v ? 6405 f02 ltc6405 shdn 0.1f 0.01f r t chosen so that r t ||r i = 100 0.1f 0.1f 0.1f 0.1f r i r i 100 100 r t 50 mini-circuits tcm4-19 mini-circuits tcm4-19 v +out v ?out v + 0.1f 0.1f 0.1f 0.1f 0.1f + ? v in ? ? 50 ? ? v tip r t ?in +out +outf +in ?out ?outf v ?outf r f c f v +outf c f r f 1.25pf 1.25pf 1.25pf 50 50 v ?in v +in (r i , r f : 0.1% resistors) *to optimize the high frequency performance for the pin configuration of the ltc6405 in the small msop package, a feedback resistance of at least 300 is recommended. package msop* qfn default values c f 1.0pf 1.8pf r i 300 200 r f 300 200 the outputs (+ out and C out) of the ltc6405 are capable of swinging from close-to-ground to typically 1 v below v + . they can source or sink up to approximately 60 ma of current. each output is designed to directly drive up to 5pf to ground. higher load capacitances should be decoupled with at least 15 of series resistance from each output. input pin protection the ltc6405 input stage is protected against differential input voltages which exceed 1.4 v by two pairs of series diodes connected back to back between + in and C in. in addition, the input pins have clamping diodes to either power supply. if the input pins are over-driven, the current should be limited to under 10 ma to prevent damage to the ic. the ltc6405 also has clamping diodes to either power supply on the v ocm , v tip and shdn pins and if driven to voltages which exceed either supply, they too, should be current limited to under 10ma. shdn pin the shdn pin is a cmos logic input with a 50 k internal pull-up resistor. if the pin is driven low, the ltc6405 pow- ers down with hi-z outputs. if the pin is left unconnected or driven high, the part is in normal active operation. some care should be taken to control leakage currents at this pin to prevent inadvertently putting the ltc6405 into shutdown. the turn-on and turn-off time between the shutdown and active states are typically less than 1s.
ltc 6405 15 6405fb for more information www.linear.com/6405 a pplications i n f or m ation general amplifier applications as levels of integration have increased and correspond- ingly, system supply voltages decreased, there has been a need for adcs to process signals differentially in order to maintain good signal to noise ratios. these adcs are typically supplied from a single supply voltage which can be as low as 3 v, and will have an optimal common mode input range of 1.25 v or 1.5 v. the ltc6405 makes interfacing to these adcs easy, by providing both single- ended to differential conversion as well as common mode level shifting. the gain to v outdiff from v inm and v inp is: v outdiff = v + out ? v ?out r f r i ? v inp ? v inm ( ) note from the above equation, the differential output volt- age (v +out C v Cout ) is completely independent of input and output common mode voltages, or the voltage at the common mode pin. this makes the ltc6405 ideally suited for pre- amplification, level shifting and conversion of single ended signals to differential output signals in preparation for driving differential input adcs.? effects of resistor pair mismatch figure 3 shows a circuit diagram which takes into consid- eration that real world resistors will not match perfectly. assuming infinite open loop gain, the differential output relationship is given by the equation: v outdiff = v + out ? v ?out ? r f r i ? v indiff + ? b b avg ? v icm ? ? b b avg ? v ocm where: r f is the average of r f1 , and r f2 , and r i is the average of r i1 , and r i2 . b avg is defined as the average feedback factor from the outputs to their respective inputs: b avg = 1 2 ? r i1 r i1 + r f1 + r i2 r i2 + r f2 ? ? ? ? ? ? ?b is defined as the difference in feedback factors: ? b = r i2 r i2 + r f2 ? r i1 r i1 + r f1 v icm is defined as the average of the two input voltages v inp and v inm (also called the input common mode voltage): v icm = 1 2 ? v inp + v inm ( ) and v indiff is defined as the difference of the input voltages: v indiff = v inp C v inm v ocm is defined as the average of the two output voltages v +out and v Cout : v ocm = v + out + v ? out 2 when the feedback ratios mismatch (?b ), common mode to differential conversion occurs. setting the differential input to zero (v indiff = 0), the de- gree of common mode to differential conversion is given by the equation: v outdiff = v + out ? v ?out v icm ? v ocm ( ) ? ? b b avg figure 3. real-world application with feedback resistor pair mismatch ? + r f2 v ?out v +out v vocm v ocm 6405 f03 r f1 r i2 r i1 + ? v inp ? + v inm v ?in v +in
ltc 6405 16 6405fb for more information www.linear.com/6405 a pplications i n f or m ation in general, the degree of feedback pair mismatch is a source of common mode to differential conversion of both signals and noise. using 1% resistors or better will mitigate most problems, and will provide about 34 db worst case of common mode rejection. using 0.1% resistors will provide about 54 db of common mode rejection. a low impedance ground plane should be used as a reference for both the input signal source and the v ocm pin. bypassing the v ocm with a high quality 0.1 f ceramic capacitor to this ground plane will further help prevent common mode signals from being converted to differential signals. there may be concern on how feedback factor mismatch affects distortion. feedback factor mismatch from using 1% resistors or better, has a negligible effect on distortion. however, in single supply level shifting applications where there is a voltage difference between the input common mode voltage and the output common mode voltage, resistor mismatch can make the apparent voltage offset of the amplifier appear worse than specified. the apparent input referred offset induced by feedback factor mismatch is derived from the above equation: v osdiff(apparent) (v icm C v ocm ) ? ?b using the ltc6405 in a single supply application on a single 5 v supply with 1% resistors, and the input common mode grounded, with the v ocm pin biased at 2.5 v, the worst case dc offset can induce 25 mv of apparent offset voltage. with 0.1% resistors, the worst case apparent offset reduces to 2.5mv. input impedance and loading effects the input impedance looking into the v inp or v inm input of figure 1 depends on whether or not the sources v inp and v inm are fully differential or not. for balanced input sources (v inp = Cv inm ), the input impedance seen at either input is simply: r inp = r inm = r i for single ended inputs, because of the signal imbalance at the input, the input impedance actually increases over the balanced differential case. the input impedance looking into either input is: r inp = r inm = r i 1? 1 2 ? r f r i + r f ? ? ? ? ? ? ? ? ? ? ? ? input signal sources with non- zero output impedances can also cause feedback imbalance between the pair of feedback networks. for the best performance, it is recommended that the input source output impedance be compensated for. if input impedance matching is required by the source, a termination resistor r1 should be chosen ( see figure 4): r1 = r inm ? r s r inm ? r s according to figure 4, the input impedance looking into figure 4. optimal compensation for signal source impedance v s + ? ? + r f r f r i r inm r s r i r2 = r s || r1 r1 chosen so that r1 || r inm = r s r2 chosen to balance r1 || r s r1 6405 f04 the differential amp ( r inm ) reflects the single ended source case, thus: r inm = r i 1? 1 2 ? r f r i + r f ? ? ? ? ? ? ? ? ? ? ? ? r2 is chosen to equal r1 || r s : r2 = r1 ? r s r1 + r s
ltc 6405 17 6405fb for more information www.linear.com/6405 ? + r f v ?out v +out v vocm v ocm 6405 f05 r f r i r i + ? v inp + ? v cm ? + v inm v ?in v +in a pplications i n f or m ation input common mode voltage range the ltc6405 s input common mode voltage ( v icm ) is defined as the average of the two input voltages, v + in , and v C in . at the inputs to the actual op amp, the range extends from v C to v + . this makes it easy to interface to a wide range of common mode signals, from ground referenced to v cc referenced signals. moreover, due to external resistive divider action of the gain and feedback resistors, the effective range of signals that can be processed is even wider. the input common mode range at the op amp inputs depends on the circuit configuration ( gain), v ocm and v cm ( refer to figure 5). for fully differential input applications, where v inp = Cv inm , the common mode input is approximately: v icm = v + in + v ?in 2 v ocm ? r i r i + r f ? ? ? ? ? ? + v cm ? r f r f + r i ? ? ? ? ? ? figure 5. circuit for common mode range manipulating the rail-to-rail input stage with v tip to achieve rail- to- rail input operation, the ltc6405 features an npn input stage in parallel with a pnp input stage. when the input common mode voltage is near v + , the npns are active while the pnps are off. when the input common mode is near v C , the pnps are active while the npns are off. at some range in the middle, both input stages are active. this hand-off operation happens automatically. in the qfn package, a special pin, v tip , is made available that can be used to manipulate the hand-off operation between the npn and pnp input stages. by default, the v tip pin is internally biased by an internal resistive divider between the supplies, developing a default 2.8 v voltage with a 5 v supply. if desired, v tip can be over-driven by an external voltage ( the thevenin equivalent resistance is approximately 17k). if v tip is pulled closer to v C , the range over which the npn input pair remains active is increased, while the range over which the pnp input pair is active is reduced. in applica- tions where the input common mode does not come close to v C , this mode can be used to further improve linearity beyond the specified performance (see figure 6). if v tip is pulled closer to v + , the range over which the pnp input pair remains active is increased, while the range over which the npn input pair is active is reduced. in applica- tions where the input common mode does not come close to v + , this mode can be used to further improve linearity beyond the specified performance. with single ended inputs, there is an input signal compo- nent to the input common mode voltage. applying only v inp ( setting v inm to zero), the input common voltage is approximately: v icm = v + in + v ?in 2 v ocm ? r i r i + r f ? ? ? ? ? ? + v cm ? r f r f + r i ? ? ? ? ? ? + v inp 2 ? r f r f + r i ? ? ? ? ? ? use the equations above to check that the v icm at the op amp inputs is within range (v C to v + ). figure 6. manipulating v tip to improve harmonic distortion hd2 v tip = open hd3 v tip = open frequency (mhz) 6405 f06 distortion (dbc) v s = 5v v ocm = v icm = 2.5v r load = 800? r i = r f = 499? v outdiff = 2v p-p single-ended input qfn package ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?110 ?100 1 100 10 hd3 v tip = 1v hd2 v tip = 1v
ltc 6405 18 6405fb for more information www.linear.com/6405 output common mode voltage range the output common mode voltage is defined as the aver- age of the two outputs: v outcm = v ocm = v + out + v ?out 2 the v ocm pin sets this average by an internal common mode feedback loop which internally forces v outcm = v ocm . the output common mode range extends from 0.5 v above v C to typically 1 v below v + . the v ocm voltage is internally set by a resistive divider between the supplies, developing a default voltage potential of 2.5v with a 5v supply. in single supply applications, where the ltc6405 is used to interface to an adc, the optimal common mode input range to the adc is often determined by the adcs refer- ence. if the adc makes a reference available for setting the input common mode voltage, it can be directly tied to the v ocm pin ( as long as it is able to drive the 19 k thevenin equivalent input impedance presented by the v ocm pin). the v ocm pin should be bypassed with a high quality ceramic bypass capacitor of at least 0.01 f to filter any common mode noise rather than being converted to dif- ferential noise and to prevent common mode signals on this pin from being inadvertently converted to differential signals by impedance mismatches both externally and internally to the ic. a pplications i n f or m ation output filter considerations and use filtering at the output of the ltc6405 is often desired to provide anti-aliasing or to improve signal to noise ratio. to simplify this filtering, the ltc6405 in the qfn package includes an additional pair of differential outputs (+outf and C outf) which incorporate an internal lowpass rc network with a C3db bandwidth of 850mhz (figure 7). these pins each have an output resistance of 50 ( toler- ance 12%). internal capacitances are 1.25pf (tolerance 15%) to v C on each filtered output, plus an additional 1.25pf ( tolerance 15%) capacitor connected between the two filtered outputs. this resistor/capacitor combination creates filtered outputs that look like a series 50 resistor with a 3.75 pf capacitor shunting each filtered output to ac ground, providing a C3 db bandwidth of 850 mhz, and a noise bandwidth of 1335 mhz. the filter cutoff frequency is easily modified with just a few external components. to increase the cutoff frequency, simply add two equal value resistors, one between + out and + outf and the other between C out and Coutf (figure 8). these resistors, in parallel with the internal 50 resistors, lower the overall resistance and therefore increase filter bandwidth. for example, to double the filter bandwidth, add two external 50 resistors to lower the series filter resistance to 25. the 3.75pf of capacitance remains unchanged, so filter bandwidth doubles. keep in mind, the series resistance also serves to decouple the outputs from load capaci- figure 7. ltc6405 internal filter topology ? + 7 +out 8 +outf 14 ?out 13 ?outf +outf ?outf 1.25pf 1.25pf 50 50 1.25pf 12 v ? 9 v ? v ? v ? 6405 f07 ltc6405 filtered output figure 8. ltc6405 filter topology modified for 2x filter bandwidth ( tw o external resistors) ? + 7 8 14 13 12 v ? 9 v ? v ? v ? 6405 f08 ltc6405 filtered output (1.7ghz) +outf ?outf 49.9 49.9 1.25pf 1.25pf 50 50 1.25pf +out +outf ?out ?outf
ltc 6405 19 6405fb for more information www.linear.com/6405 a pplications i n f or m ation tance. the outputs of the ltc6405 are designed to drive 5pf to ground, so care should be taken to not lower the effective impedance between + out and + outf or Cout and Coutf below 15. to decrease filter bandwidth, add two external capacitors, one from + outf to ground, and the other from Coutf to ground. a single differential capacitor connected between +outf and C outf can also be used, but since it is being driven differentially it will appear at each filtered output as a single-ended capacitance of twice the value. to halve the filter bandwidth, for example, two 3.9 pf capacitors could be added ( one from each filtered output to ground). alternatively, one 1.8 pf capacitor could be added between the filtered outputs, which also halves the filter bandwidth. combinations of capacitors could be used as well; a three capacitor solution of 1.2 pf from each filtered output to ground plus a 1.2 pf capacitor between the filtered outputs would also halve the filter bandwidth (figure 9). noise considerations the ltc6405s input referred voltage noise is 1.6nv/ hz. its input referred current noise is 2.4 pa/ hz . in addition to the noise generated by the amplifier, the surrounding feedback resistors also contribute noise. a noise model is shown in figure 10. the output noise generated by both the amplifier and the feedback components is governed by the equation: e no = e ni ? 1+ r f r i ? ? ? ? ? ? ? ? ? ? ? ? 2 + 2 ? i n ? r f ( ) 2 + 2 ? e nri ? r f r i ? ? ? ? ? ? ? ? ? ? ? ? 2 + 2 ? e nrf 2 a plot of this equation, and a plot of the noise generated by the feedback components for the ltc6405 is shown in figure 11. figure 9. ltc6405 filter topology modified for 1/2x filter bandwidth (three external capacitors) ? + 7 8 14 13 12 v ? 9 v ? v ? v ? 6405 f09 ltc6405 filtered output (425mhz) 1.25pf 1.25pf 50 50 1.25pf 1.2pf 1.2pf 1.2pf +outf ?outf +out +outf ?out ?outf figure 10. noise model of the ltc6405 figure 11. ltc6405 output spot noise vs spot noise contributed by feedback network alone ? + e no 2 r f v ocm e nri 2 r f r i r i e nrf 2 e nri 2 e ncm 2 e ni 2 e nrf 2 i n +2 i n ?2 6405 f10 r i = r f () 10 0.1 1 10 100 100 1000 10000 6405 f11 total (amplifier and feedback network) output noise feedback network noise alone nv/ hz
ltc 6405 20 6405fb for more information www.linear.com/6405 a pplications i n f or m ation the ltc6405 s input referred voltage noise contributes the equivalent noise of a 155 resistor. when the feedback network is comprised of resistors whose values are less than this, the ltc6405s output noise is voltage noise dominant (see figure 11): e no e ni ? 1+ r f r i ? ? ? ? ? ? feedback networks consisting of resistors with values greater than about 200 will result in output noise which is resistor noise and amplifier current noise dominant. e no 2 ? i n ? r f ( ) 2 + 1+ r f r i ? ? ? ? ? ? ? 4 ? k ? t ? r f lower resistor values (<100) always result in lower noise at the penalty of increased distortion due to increased loading of the feedback network on the output. higher resistor values ( but still less than <500) will result in higher output noise, but typically improved distortion due to less loading on the output. the optimal feedback resis- tance for the ltc6405 runs in between 100 to 500. the differential filtered outputs + outf and C outf will have a little higher noise than the unfiltered outputs (due to the two 50 resistors which contribute 0.9nv/ hz each), but can provide superior signal-to-noise due to the output noise filtering. layout considerations because the ltc6405 is a very high speed amplifier, it is sensitive to both stray capacitance and stray inductance. in the qfn package, three pairs of power supply pins are provided to keep the power supply inductance as low as possible to prevent any degradation of amplifier 2nd harmonic performance. it is critical that close attention be paid to supply bypassing. for single supply applications it is recommended that high quality 0.1 f surface mount ceramic bypass capacitor be placed directly between each v + and v C pin with direct short connections. the v C pins should be tied directly to a low impedance ground plane with minimal routing. for dual ( split) power supplies, it is recommended that additional high quality , 0.1 f ceramic capacitors are used to bypass v + to ground and v C to ground, again with minimal routing. for driving large loads (<200), additional bypass capacitance may be needed for optimal performance. keep in mind that small geometry (e.g., 0603) surface mount ceramic capacitors have a much higher self resonant frequency than do leaded capacitors, and perform best in high speed applications. any stray parasitic capacitances to ground at the summing junctions, +in and C in, should be minimized. this becomes especially true when the feedback resistor network uses resistor values >500 in circuits with r f = r i . always keep in mind the differential nature of the ltc6405, and that it is critical that the load impedances seen by both outputs (stray or intended), should be as balanced and symmetric as possible. this will help preserve the natural balance of the ltc6405, which minimizes the generation of even order harmonics, and improves the rejection of common mode signals and noise. it is highly recommended that the v ocm pin be bypassed to ground with a high quality ceramic capacitor whose value exceeds 0.01 f. this will help stabilize the common mode feedback loop as well as prevent thermal noise from the internal voltage divider and other external sources of noise from being converted to differential noise due to divider mismatches in the feedback networks. it is also recommended that the resistive feedback networks be comprised of 1% resistors ( or better) to enhance the output common mode rejection. this will also prevent v ocm input referred common mode noise of the common mode amplifier path ( which cannot be filtered) from being converted to differential noise, degrading the differential noise performance. feedback factor mismatch has a weak effect on distortion. using 1% or better resistors will limit any mismatch from impacting amplifier linearity. however, in single supply level shifting applications where there is a voltage differ- ence between the input common mode voltage and the output common mode voltage, resistor mismatch can make the apparent voltage offset of the amplifier appear worse than specified.
ltc 6405 21 6405fb for more information www.linear.com/6405 interfacing the ltc6405 to a/d converters rail-to-rail input and fast settling time make the ltc6405 ideal for interfacing to low voltage, single supply, differ- ential input adcs. the sampling process of adcs create a sampling glitch caused by switching in the sampling capacitor on the adc front end which momentarily shorts the output of the amplifier as charge is transferred between the amplifier and the sampling capacitor. the amplifier must recover and settle from this load transient before this acquisition period ends for a valid representation of the input signal. in general, the ltc6405 will settle much more quickly from these periodic load impulses than from a 2 v input step, but it is a good idea to place an r-c filter network between the differential outputs of the ltc6405 and the input of the adc to help absorb the charge injection that comes out of the adc from the sampling process. the capacitance of the filter network serves as a charge reservoir to provide high frequency charging during the sampling process, while the resistors of the filter network are used to dampen and attenuate any charge kickback from the adc. the selection of the r-c time constant is trial and error for a given adc, but the following guidelines are recommended: choosing too large of a resistor in the decoupling network leaving insufficient settling time will create a voltage divider between the dynamic input imped- ance of the adc and the decoupling resistors. choosing too small of a resistor will possibly prevent the resistor from properly dampening the load transient caused by the sampling process, prolonging the time required for settling. in 16- bit applications, this will typically require a minimum of 11 r-c time constants. it is recommended that the capacitor chosen have a high quality dielectric (such as c0g multilayer ceramic). a pplications i n f or m ation figure 12. interfacing the ltc6405 to an adc 0.1f ? + 1 shdn 5 6 ?in 7 +out 8 +outf 16 15 +in nc 14 ?out 13 ?outf +ina ?ina 200 2 v + 3 v ? v + v ? 5v v ocm v ocm 12 v ? 11 v + 10 v + 9 v ? v ? v ? 6405 f12 ltc6405 ltc2208 v in , 2v p-p shdn 200 200 100 200 0.1f 20 20 5v 4 0.1f 0.1f control gnd v dd v cm d15 ? ? d0 0.1f 4.7pf 4.7pf 4.7pf 3.3v 1f 1f v tip 1.8pf 1.8pf 1.25pf 1.25pf 1.25pf 50 50 2.2f
ltc 6405 22 6405fb for more information www.linear.com/6405 attenuating and level shifting a single-ended 5v signal to a differential 2v p-p signal at a 1.25v common mode ltc2207 3.3v 6405 ta03 r1 51.1? 5v sine wave (10v p-p ) centered at 0v r2 51.1? r3, 100? r4, 100? c1, 2.7pf c2, 2.7pf 2v p-p diff output level-shifted to 1.25v v in r5 511? r6 511? + ? ? + 5v ltc6405 v cm = 1.25v 2.2f t ypical a pplication
ltc 6405 23 6405fb for more information www.linear.com/6405 p ackage description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. msop (ms8e) 0911 rev j 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 1 2 3 4 4.90 0.152 (.193 .006) 8 8 1 bottom view of exposed pad option 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 1.68 (.066) 1.88 (.074) 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 1.68 0.102 (.066 .004) 1.88 0.102 (.074 .004) 0.889 0.127 (.035 .005) recommended solder pad layout 0.65 (.0256) bsc 0.42 0.038 (.0165 .0015) typ 0.1016 0.0508 (.004 .002) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref ms8e package 8-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1662 rev j)
ltc 6405 24 6405fb for more information www.linear.com/6405 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions 1.45 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 bottom view?exposed pad 1.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 0.05 3.50 0.05 0.70 0.05 0.00 ? 0.05 (ud16) qfn 0904 0.25 0.05 0.50 bsc package outline ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691 rev ?) p ackage description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
ltc 6405 25 6405fb for more information www.linear.com/6405 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h istory rev date description page number b 02/13 changed operating voltage upper range from 5.5v to 5.25v 1, 3, 4 changed voltage max spec from 0.4v to 0.45v 3 (revision history begins at rev b)
ltc 6405 26 6405fb for more information www.linear.com/6405 ? linear technology corporation 2012 lt 0213 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/6405 t ypical a pplication part number description comments lt1993-2/lt1993-4/ lt1993-10 800mhz/900mhz/700mhz low distortion, low noise differential amplifier/adc driver a v = 2v/v / a v = 4v/v / a v = 10v/v, nf = 12.3db/14.5db/ 12.7db, oip3 = 38dbm/40dbm/40dbm at 70mhz lt1994 low noise, low distortion fully differential input/output amplifier/driver low distortion, 2v p-p , 1mhz: C94dbc, 13ma, low noise: 3nv/ hz ltc6400-8/ltc6400-14/ ltc6400-20/ltc6400-26 1.8ghz low noise, low distortion, differential adc driver 300mhz if amplifier, a v = 20db/26db ltc6401-8/ltc6401-14/ ltc6401-20/ltc6401-26 1.3ghz low noise, low distortion, differential adc driver 140mhz if amplifier, a v = 20db/26db lt6402-6/lt6402-12/ lt6402-20 300mhz/300mhz/300mhz low distortion, low noise differential amplifier/adc driver a v = 6db/a v = 12db/a v = 20db, nf = 18.6db/15db/12.4db, oip3 = 49dbm/43dbm/51dbm at 20mhz ltc6404-1/ ltc6404-2/ ltc6404-4 600mhz low noise, low distortion, differential adc driver 1.5nv/ hz noise, C90dbc distortion at 10mhz ltc6406 3 ghz low noise, 3v , rail - to- rail input differential amplifier/ driver 1.6nv/ hz noise, C70dbc distortion at 50mhz, 18ma, 3 v supply ltc6411 low power differential adc driver/dual selectable gain amplifier 16ma supply current, imd3 = C83dbc at 70mhz, a v = 1, C1, or 2 lt6600-2.5/lt6600-5/ LT6600-10/lt6600-20 ve ry low noise, fully differential amplifier and 4th order filter 2.5mhz/5mhz/10mhz/20mhz integrated filter, 3v supply, so-8 package ltc6403-1 200mhz low noise, low power differential adc driver C95dbc distortion at 3mhz, 10.8ma supply current dc-coupled level shifting of demodulator output ltc2249 14-bit adc 80mhz sample clock 3.3v 6405 ta02 10dbm 15nh r9 10? c8 4.7pf c7 4.7pf c6 4.7pf c2 4.7pf c1 4.7pf rf in 900mhz ?7dbm r10 10? r7 49.9? r5, 324? r6, 324? c5, 10pf c4, 10pf diff output z 130? | | 2.5pf dc level 1.5v dc level 3.8v gain: 14db input nf: 11db oip3: 44dbm at 30mhz gain: 3db input nf: 13db oip3: 31dbm r8 49.9? identical q channel 5v 5pf 65? 5pf 65? ? + + ? 5v ltc6405 5v i 5v 5pf 65? 5pf 65? 5v q 5v lt5575 4.7pf lo odbm 3.9pf 15nh v ocm = 1.5v v cm r elate d p arts

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